1. Field
The present invention relates to semiconductor wafer process, and more specifically semiconductor wafer backside grinding.
2. Discussion of Related Art
Wafer backside grinding (BSG) is conventionally employed to reduce the original thickness of semiconductor wafer after device fabrication and passivation. The profile of a wafer is reduced to a desired thickness suitable for assembling dies (obtained after wafer singulation step) on substrate packages. Backside grinding may induce subsurface damage and intrinsic stress to the wafer. Wafer backside is polished to remove the subsurface damage and to recover the wafer strength from earlier induced stress. However a smooth die backside makes cosmetic defects introduced during subsequent processes such as assembly and test on the die backside surface more pronounced. Dies with visible cosmetic defects are typically rejected and cause low yield.
A semiconductor wafer may include dies of various performance specifications catered for different product lines and market segments. A wafer may undergo different wafer preparation process steps depending upon, for example, the end products the dies are to be assembled. Hence, some dies on a wafer may need to be discarded and cause lower yield if the demand for the particular end product is low.
Examples are presented to illustrate the points in above paragraph. Wafers from fabrication plants may or may not undergo backside metallization (BSM) process step depending on the product demand of certain dies obtained from the wafers. Backside metallization on wafer backside enables a lower thermal junction-to-case resistance (R0JC) to be attained. Dies intended for high-end applications typically undergo backside metallization. No touch-up of the wafer backside, such as smooth backside grinding, may be required as typically the backside of the dies will not be visible to end users. Instead, solder thermal interface material (STIM) may be applied on the backside of dies for high-end applications to provide low thermal junction-to-case resistance.
On the other hand, backside metallization may not be required for some wafers. Dies obtained from wafers without backside metallization are typically intended for middle and lower end applications. Wafers not subject to backside metallization process step may undergo backside grinding such as smooth grinding or wafer thinning before undergoing wafer preparation steps. Polymeric thermal interface material (PTIM) may be applied to the die backside and will result in higher thermal junction-to-case resistance relative to STIM.